Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling a conductive material in trenches etched into the dielectric layers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts.
The filling of a conductive material into features, such as vias or trenches, configured for contacts, elongated lines or contacts, can be carried out by electrodeposition, also known as plating or electrochemical deposition (ECD). In an electrodeposition or electroplating process, a conductive material, such as copper, is deposited over the substrate surface, including into such features. However, the substrate surface may include a plurality of features having different sizes. In existing deposition technologies, the features are typically overfilled with the conductive material to ensure that each feature, regardless of its width, is completely filled with the conductive material. This overfilling results in a non-planar excess conductive layer on the surface of the substrate, which includes steps or recesses over the large width features. After deposition of conductive material, a material removal technique is employed to planarize and remove the excess conductive material or overburden from the top surface, leaving conductive material only in the features or cavities. A chemical mechanical polishing (CMP) process is typically employed to remove the excess conductive material on the top surface of the substrate. Thickness of the excess layer is generally 1.2-1.5 times the depth of the large width features, which, as noted above, varies.
An interconnect network is made of many levels of metal layers formed on top of one another. Generally, initial metal layers, such as, for example, M1, M2, which form the bottom of the metal stack, have the features with the smaller depths. Upper metal layers, such as, for example, M3 . . . M10, may include gradually increasing depths per layer, resulting in thicker excess conductive layers at higher levels, due to the deeper features (e.g., vias, trenches, etc.) at those higher levels.
FIGS. 1 and 2 illustrate two different metal layers or metallization levels of exemplary multilayer semiconductor structures. FIG. 1 shows a substrate 10a having a first copper layer 12a deposited on a surface 14a of the substrate 10a, filling the features, such as the illustrated small features 16a and large features 18a, formed in the surface. As shown, the first copper layer 12a includes an excess layer 20a, which is non-planar and should ultimately be planarized for subsequent processing. For example, if the depth da of the features 16a, 18a is 0.5 micron (μm), the thickness ta of the excess layer 20a can be 0.75 micron (μm). FIG. 2 shows another substrate 10b, including a second copper layer 12b deposited on a surface 14b of the substrate 10b to fill the features, such as small features 16b and large features 18b, formed in the surface. The second copper layer 12b is a copper layer forming an upper metal layer of a multilayer semiconductor structure. While illustrated in FIG. 2 as being in a different wafer, the skilled artisan will understand that the structure of FIG. 2 can represent an upper metal level of a multilayer structure, such as the one shown in FIG. 1, or a metal layer of a different multilayer structure, in a different wafer or the same wafer, in a different batch or the same batch. As shown, the second copper layer 12b is non-planar and dishes, especially in the area over the wide feature 18b. The second copper layer 12b includes an excess layer 20b having a thickness tb. The feature depth db of the substrate 10b shown in FIG. 2 is larger than the feature depth da of the substrate 10a shown in FIG. 1 (db>da) If the depth of the features db is, for example, 2 microns (μm), the thickness tb of the excess layer 20b can be 3 microns (μm).
Chemical mechanical polishing (CMP) of these two substrates or wafers 10a, 10b using the same CMP system can be a complicated and costly process. Because of the thin excess layer 20a on the substrate 10a shown in FIG. 1, the substrate 10a will be planarized more quickly than the substrate 10b shown in FIG. 2 because tb>ta. The substrate 10b, shown in FIG. 2, with the thicker excess layer 20b will take a longer time to planarize. As such, in a process environment involving many wafers with different excess layer thicknesses, wafers with thicker excess layers will take more time and this would make it impractical to mix wafers with different feature depths in the same copper removal lot. Even in different lots, additional expense would be entailed in tailoring a single CMP machine to polish these different thicknesses. From a practical standpoint, the manufacturer will employ several different CMP tools to polish wafers having layers of different thicknesses, and will have to configure the CMP tools differently.